A crystal oscillator, such as a temperature compensated crystal oscillator (TCXO), provides a reference frequency for various phase-locked loops (PLLs) inside a typical radio frequency integrated circuit (RFIC), as well as providing clocks for various processors. These PLLs are necessary blocks for radios, for example, Wi-Fi, cellular, global navigation satellite system (GNSS), and Bluetooth.
As communications systems evolve, there is a need to develop very low-noise PLLs to synthesize very low-noise local oscillator signals used in a transmitter and/or a receiver of a radio. A higher reference frequency for a PLL generally improves the phase noise of the PLL. Therefore, it is desirable to have the option of using twice the crystal oscillator frequency as a reference clock to the PLL. The reference clock is typically implemented by a frequency doubling circuit that may be part of, or outside the PLL, using both the rising edge and the falling edge of the reference clock. For such applications, it is important that the frequency doubling circuit has an input clock that is as close to symmetrical, or 50% duty cycle, as possible. This reduces the level of the unwanted sub-harmonics in the double-frequency output from the frequency doubling circuit.